Use of selective ozone TEOS oxide to create variable thickness layers and spacers

ABSTRACT

A process for selectively depositing a silicon oxide layer onto silicon substrates of different conductivity types is disclosed. The silicon oxide layer is formed by the ozone decomposition of TEOS at relatively low temperatures and relatively high pressures. Use of the process to produce layers, spacers, memory units, and gates is also disclosed, as well as the structures so produced.

FIELD OF THE INVENTION

[0001] This invention relates to the fabrication of semiconductordevices. More particularly, this invention relates to selectivedeposition of silicon oxide onto silicon substrates.

BACKGROUND OF THE INVENTION

[0002] Optimization of semiconductor fabrication sometimes requires athicker nonconducting film on some components than on other components.For example, a thick oxide layer or spacer on a P-type silicon wordlinemay be desired because the boron implants diffuse readily to an adjacentlayer. In contrast, an N-type polysilicon component may optimallyrequire a thinner oxide layer or spacer since N-type dopants do notdiffusse as readily. A simple process that provides different thicknessnonconducting films and spacers is desired in semiconductor fabrication.

[0003] Forming oxide layers and spacers of different thicknesses overvarying silicon subates using current methods requires the applicationof a first mask over select parts of the semiconductor device and thendepositing a layer of silicon oxide over the unmasked parts of thesemiconductor device. The first mask is then removed and a second maskis applied over the parts that have been coated with the first siliconoxide; layer leaving other parts unmasked. Subsequently, a secondsilicon oxide layer is deposited on the unmasked parts. Finally, an etchis used to remove silicon oxide from select surfaces, leaving behind anoxide layer or spacers where desired. This process adds a number ofsteps to the manufacturing procedures thereby increasing the complexityof the fabrication. As such, semiconductors are typically manufacturedoxide with oxide layers or spacers of an intermediate thickness thatwill work acceptably, although not optimally, for either P-type orN-type polysilicons substrate.

[0004] A halhnark of the current invention is the provision of a processthat selectively deposits silicon oxide based on the conductivity typeof the underlying silicon substrate.

SUMMARY OF THE INVENTION

[0005] The current invention is a method for selectively depositingsilicon oxide onto a silicon-comprising surface wherein the selectivityis based on the conductivity type of the silicon. In one embodiment, theinvention is a semiconductor processing method for selectivelydepositing silicon oxide onto silicon, the method comprising the stepsof: (i) providing a silicon-comprising substrate having exposed regionsof different type conductivity; (ii) contacting the substrate with ozoneand tetraethylorthosilicate (TEOS) gases; and, (iii) reacting the ozoneand TEOS in contact with the substrate to selectively deposit siliconoxide onto the substrate, such that, compared to the deposition rate onexposed regions of nonoped silicon, the silicon oxide deposits at afaster rate on exposed regions of P-type silicon and at a slower rate onexposed regions of N-type silicon.

[0006] Another embodiment of the invention is a method for forming anoxide layer of varying thickness on a silicon-comprising substrate, themethod comprising the steps of: (i) providing the silicon-comprisingsubstrate having a surface and comprising at least a first and secondregion of different type conductivity; and (ii) depositing silicon oxideonto the substrate in a single process step, to form an oxide layer overthe first and second conductivity regions; whereby oxide layer overlyingthe first conductivity region has a first thickness and the oxide layeroverlying the second conductivity region has a second thickness that isgreater than the first thickness.

[0007] Another embodiment of the invention is a semiconductor processingmethod of forming spacers of variable thickness, the method comprisingproviding a silicon-comprising substrate having a surface comprising atleast one first P-type silicon structure or protrusion and at least onesecond structure or protrusion, provided that: (1) when the firstprotrusion comprises P-type or non-doped silicon, then the secondstructure or protrusion comprises either non-doped silicon or N-typesilicon; and (2) when the first protrusion comprises non-doped silicon,then the second structure or protrusion comprises N-type silicon. Next,TEOS is decomposed with ozone to selectively deposit silicon oxide overthe silicon surface and both the first protrusion and the secondprotrusion, such that a greater thickness of silicon oxide is depositedon the first protrusion than on the second protrusion. Finally, thedeposited silicon oxide is etched to remove the oxide from select areasand leave silicon oxide as a layer or as formed spacers of variablethickness around the first protrusion and the second protrusion.

[0008] Another embodiment of the invention is a semiconductor processingmethod of forming wordlines with an oxide layer or formed spacers ofvariable thickness. The method of this embodiment comprises providing asilicon-comprising substrate having a surface comprising at least onefirst wordline comprising P-type silicon and at least one secondwordline comprising N-type silicon. Next, TEOS is decomposed with ozoneto selectively deposit silicon oxide over the substrate surface and overboth the first wordline and the second wordline, such that a greaterthickness of silicon oxide is deposited on the first wordline than onthe second wordline. Then, the silicon oxide deposited on the substrateduring the reaction step is etched to provide a silicon oxide layer orformed spacers of variable thickness around the first wordline and thesecond wordline.

[0009] Another embodiment of the invention is a semiconductor processingmethod of forming gates with spacers of variable thickness. The methodofthis embodiment comprises providing a silicon-comprising substratehaving a surface comprising at least one first gate comprising P-typesilicon-comprising material and at least one second gate comprisingN-type silicon-comprising material. Next, TEOS is decomposed with ozoneto selectively deposit silicon oxide over the substrate surface and overboth the first gate and the second gate, such that a greater thicknessof silicon oxide is deposited on the first gate than on the second gate.Then, the silicon oxide deposited on the substrate during the reactionstep is etched to leave a silicon oxide layer or formed spacers ofvariable thickness around the first gate and the second gate.

[0010] Another embodiment of the invention is a memory device comprisingat least a first wordline comprising P-type silicon-comprising materialand at least a second wordline comprising N-type silicon-comprisingmaterial, wherein both the first wordline and the second wordline havenonconductive spacers comprising silicon oxide wherein the nonconductivelayer or formed spacer for the first wordline is thicker than thenonconductive layer or spacer for the second wordline.

[0011] Another embodiment of the invention is a multi-gate semiconductordevice comprising at least one gate comprising (i) P-typesilicon-comprising material, (ii) at least one second gate comprisingN-type silicon-comprising material and, (iii) layer or a nonconductivelayer or formed spacers around each of the first and second gates,wherein the nonconductive layer or spacer is thicker for the first gatethan for the second gate.

BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Preferred embodiments of the invention are described below withreference to the following accompanying drawings, which are forillustrative purposes only. Throughout the following views, referencenumerals will be used in the drawings, and the same reference numeralswill be used throughout the several views and in the description toindicate same or like parts.

[0013]FIG. 1 is a bar graph comparing deposition rates and layerthicknesses for the selective deposition of TEOS decomposed by ozone onsiliconomprising substrates that have different conductivities.

[0014]FIG. 2 is a cross-sectional view of a silicon-comprismig substratehaving an N-type silicon-comprising protrusion and a P-typesilicon-comprising protrusion.

[0015]FIG. 3 shows the substrate of FIG. 2 following selectivedepositing of silicon oxide.

[0016]FIG. 4 shows the substrate of FIG. 3 following an etch processingstep.

[0017]FIG. 5 shows a scanning electromicrograph (SEM) of a siliconsubstrate demonstrating the selective deposition of silicon oxide ontosilicon substrates of different conductivity types.

DETAILED DESCRIPTION

[0018] In the following detailed description, references are made to theaccompanying drawings which form a part hereof, and in which is shown byway of illustration specific embodiments in which the invention may bepracticed. These embodiments are described in sufficient detail toenable those skilled in the art to practice the invention, and it is tobe understood that other embodiments may be utilized and thatstructural, logical and electrical changes may be made without departingfrom the spirit and scope of the present invention.

[0019] The terms “wafer” or “substrate” used in the followingdescription include any semiconductor-based structure having an exposedpolysilicon or other silicon-comprising surface in which to form thesilicon oxide deposition layer of this invention. Wafer and substrateare to be understood as including silicon-on-insulator (SOI) orsilicon-on-sapphire (SOS) technology, doped and undoped semiconductors,epitaxial layers of silicon supported by a base semiconductorfoundation, and other semiconductor structures. Furthermore, whenreferences made to a wafer or substrate in the following description,previous process steps may have been used to form regions or junctionsin the base semiconductor structure or foundation.

[0020]FIG. 1 is a bar graph showing selective deposition of siliconoxide using ozone/TEOS on silicon that has been doped with an N-typedopant (arsenic; center bar) or a P-type dopant (boron; right bar) ornot doped (left bar) The substrate is composed of a single crystalsilicon wafer, which has been implanted with the specified dopant. Thesurface was subjected to a hydrogen fluoride dip prior to the ozone/TEOSdeposition processing. A blanket layer of silicon oxide was deposited onthe wafer surface by ozone decomposition of TEOS at a temperature ofabout 400° C. and a pressure of about 300 torr. Under these reactionconditions, about five liters per minute of oxygen, containing about 10%by weight ozone, and about 350 milligrams per minute of TEOS weresupplied to the deposition vessel.

[0021] As shown in FIG. 1, a P-type implant, in this case borondifluoride, in a silicon-comprising substrate (polysilicon) obtains ahigher deposition rate (approximately 22% faster) of oxide and reaches agreater deposition thickness for a given time than non-doped silicon. Incontrast, an N-type implant, in this case arsenic, in asilicon-comprising substrate (polysilicon) retards the deposition rate(approximately 14% slower) of oxide as compared to non-doped silicon andresults in a lower thickness. Similar results are obtained when theN-type implant is phosphorous. As such, the oxide deposits approximately33% faster on P-type silicon than on N-type silicon. The selectivityeffect is more pronounced at higher concentrations of dopant.Additionally, the selectivity increases as the reaction temperaturedecreases and/or the reaction pressure increases.

[0022] FIGS. 2-4 shows a typical embodiment of the process of thisinvention, in which two non-abutting structures or protrusions 21, 22are arrayed on a silicon-comprising substrate 20 such as single crystalsilicon, epitaxial silicon or polysilicon. Protrusion 21 has a P-typedoped silicon layer 23. Protrusion 22 has an N-type doped silicon layer24. Protrusions 21 and 22 each have a metalized film 25, such astungsten silicide, arrayed atop the doped polysilicon layers 23 and 24,respectively.

[0023] The substrate 20 (single crystal) and protrusions 21 and 22 arecontacted with gaseous ozone and gaseous TEOS under conditions where asilicon oxide layer 30 is deposited over the substrate and protrusionsas shown in FIG. 3. At the proper reaction conditions, the silicon oxidewill deposit selectively onto the substrate and protrusions in a singleprocess step. The selectivity of this single process step avoids thenecessity of masking and performing multiple photolithographic steps toform a suitably thick oxide layer or spacer 30 over the component layersof the protrusions 21, 22 and the substrate 20. As shown a thicker layer26 is formed over the P-type layer 23. An intermediate thickness layer27 is deposited over non-doped silicon substrate 20. A thinner layer 24is deposited over the N-type silicon layer 24. An intermediate thicknesslayer 29 is deposited over metalized silicide film layer 25.

[0024] Appropriate reaction conditions for the selective deposition ofsilicon oxide over materials with different type doping is similar tothe reaction conditions used in conventional methods to obtain selectivedeposition on silicon versus silicon nitride. Such reaction conditionsare known in the art as shown in U.S. Pat. No. 5,665,644, incorporatedherein by reference. Typically, the reaction temperature is greater thanabout 200° C. up to about 500° C., preferably up to about 400° C.Generally, the selectivity of the deposition is more pronounced at lowerreaction temperatures. The reaction pressure is at least about 10 torr,preferably at least about 300 torr up to about atmospheric pressure,more preferably up to about 600 torr.

[0025] An exemplary reaction supplies about five liters per minute ofoxygen containing about 10% by weight ozone and about 350 milligrams perminute TEOS. The oxygen: ozone ratio may typically vary from about 2parts oxygen: 1 part ozone to about 20 parts oxygen: 1 part ozone. Theozone: TEOS ratio typically varies from about 0.5:1 to about 200:1.Reaction times will vary depending on the desired thickness of thedeposited layer, generally about 2-3 minutes.

[0026] Optionally, the surface to receive the oxide layer may be wetcleaned in a dip prior to depositing the oxide layer. A hydrofluoricacid (HF) wet-clean dip provides a marginal enhancement of theselectivity of the deposition. Other wet-clean dips, such as sulfuiricacid or non-fluorine type etchants, have not been found to enhance theselectivity of the deposition and may negatively affect the subsequentdeposition.

[0027] Following the deposition of the oxide layer 30, the portion ofthe oxide layer 27 overlying the substrate 20 is selectively etched toexpose the substrate 20, resulting in the structure of FIG. 4 having theoxide layers 26,28 remaining over the protrusions 21,22, respectivelyAny suitable oxide etching method may be used to remove the oxide layer27 and expose the substrate 20. Preferably, the method provides ananisotropic etch. Suitable etching methods include directional methodssuch as reactive ion etching (RIE). An exemplary etching process is byRIE using a mixture of carbon tetrafluoride (CF₄) at a flow of about 15standard cubic centimeters per minute (sccm), and methylene trifluoride(CHF₃) at 25 sccm for thirty seconds at about 200 millitorr and a powerof 100 watts.

[0028] In one preferred embodiment, the protrusions 21, 22 of FIG. 2represent wordlines of different conductivity. In this embodiment, layer23 represents a wordline comprising P-doped silicon and layer 24represents a wordline comprising N-doped silicon. These wordlines can beincorporated into a memory unit, such as a dynamic random access memory(DRAM), by any suitable means known in the art.

[0029] In another preferred embodiment of the invention, the protrusions21, 22 represent a dual gate structure. In this embodiment, layer 23 inFIG. 2 represents a gate comprising P-doped silicon and layer 24represents a gate compsing N-doped polysilicon.

[0030] In another embodiment of the invention, blanket layers of oxideusing ozone/TEOS deposition processing are deposited over a siliconsubstrate having differentially doped areas. FIG. 5 is a SEMphotomicrograph showing a cross-section of a silicon substrate 100 uponwhich this invention has been enacted. A transistor 114 is disposed onthe surface of the substrate 100. The portion 102 of substrate 100 hasbeen doped with a P-type conductivity enhancing dopant such as boron,and portion 104 of the substrate 100 has been doped with an N-typedopant such as phosphorus. The intermediate (dark) layer 106 immediatelyabove the substrate 100 and the transistor 114 is an oxide layer 106formed from an ozone/TEOS deposition. The outermost (white) layer 112above the oxide layer 106 is a deposited titanium nitride cap layer. Asshown in FIG. 5, the silicon oxide layer 106 deposited as asignificantly thicker layer l08 over the P-type doped portion 102 of thesilicon substrate 100 compared to the thinner layer 110 deposited overthe N-type doped portion 104 of the silicon substrate 100.

[0031] The methods and devices of the current invention are usefulwhenever semiconductors are fabricated with silicon-comprising regionsor structures having different type conductivities. Examples of usefulapplications include memory arrays, such as DRAM and static randomaccess memory (SRAM), logic circuitry, and combinations of memory andlogic, such as a system-on-chip array.

[0032] In compliance with the statute, the invention has been describedin language more or less specific as to structural and methodicalfeatures. It is to be understood, however, that the invention is notlimited to the specific features shown and described, since the meansherein disclosed comprise preferred forms of putting the invention intoeffect. The invention is, therefore, claimed in any of its forms ormodifications within the proper scope of the appended claimsappropriately interpreted in accordance with the doctrne of equivalents.

The invention claimed is:
 1. A method for selectively depositing siliconoxide onto a silicon-comprising substrate, the method comprising thesteps of: providing the silicon-comprising substrate having exposedregions of different type conductivity; and reacting ozone andtetraethylorthosilicate in contact with the substrate to selectivelydeposit silicon oxide onto the substrate, whereby, compared to exposedregions of non-doped silicon, the silicon oxide deposits at a fasterrate on exposed regions of P-type silicon and at a slower rate onexposed regions of N-type silicon.
 2. A method for selectivelydepositing silicon oxide onto a silicon-comprising substrate, the methodcomprising the steps of: providing the silicon-comprising substratehaving exposed regions of different type conductivity; and reactingozone and tetraethylorthosilicate in contact with the substrate toselectively deposit silicon oxide onto the substrate, whereby, comparedto exposed regions of non-doped silicon, the silicon oxide deposits at afaster rate on exposed regions of P-type silicon and at a slower rate onexposed regions of N-type silicon, wherein the reaction occurs at atemperature up to about 500° C. and a pressure of at least about 10torr.
 3. The method of claim 2, wherein the reaction occurs at atemperature up to about 400° C.
 4. The method of claim 2, wherein thereaction occurs at a pressure of at least about 300 tort.
 5. Asemiconductor processing method of forming spacers of variablethickness, the method comprising the steps of: providing asilicon-comprising substrate having a surface comprising at least onefrrst conductive region comprising either P-type silicon or non-dopedsilicon and at least one second conductive region, provided that: (1)when the first conductive region comprises P-type silicon, then thesecond conductive region comprises either non-doped silicon or N-typesilicon; and, (2) when the first conductive region comprises non-dopedsilicon, then the second conductive region comprises N-type silicon;depositing silicon oxide, in a single process step, to form a layer overthe silicon-comprising substrate and both the first conductive regionand the second conductive region, whereby a greater thickness of siliconoxide is deposited on the first conductive region than on the secondconductive region; and etching the silicon oxide deposited on thesubstrate to remove silicon oxide from the surface of the substrate,whereby the silicon oxide layers remaining on the first and secondconductive regions provides a layer of variable thickness around thefirst conductive region and the second conductive region.
 6. Asemiconductor processing method of forming spacers of variablethickness, the method comprising the steps of: providing asilicon-comprising substrate having a surface comprising at least onefirst conductive region comprising either P-type silicon or non-dopedsilicon and at least one second conductive region, provided that: (1)when the first conductive region comprises P-type silicon, then thesecond conductive region comprises either non-doped silicon or Ntypesilicon; and, (2) when the first conductive region comprises non-dopedsilicon, then the second conductive region comprises N-type silicon;decomposing tetraethylorthosilicate with ozone to selectively depositsilicon oxide over the silicon surface and over both the firstconductive region and the second conductive region, whereby a greaterthickness of silicon oxide is deposited on the first conductive regionthan on the second conductive region; and, etching the silicon oxidedeposited on the substrate to remove silicon oxide from the surface ofthe substrate, whereby the silicon oxide layers remaining on the firstand second conductive regions provides a layer of variable thicknessaround the first conductive region and the second conductive region. 7.A semiconductor processing method of forining spacers of variablethickness, the process comprising the steps of: providing asilicon-comprising substrate having a surface comprising at least onefirst conductive region comprising either P-type silicon or non-dopedsilicon and at least one second conductive region, provided that: (1)when the first conductive region comprises P-type silicon, then thesecond conductive region comprises either non-doped silicon or N-typesilicon; and, (2) when the first conductive region comprises non-dopedsilicon, then the second conductive region comprises N-type silicon;contacting silicon-comprising substrate with ozone andtetraethylorthosilicate whereby the first conductive region and thesecond conductive region are in intimate contact with the ozone and thetetraethylorthosilicate; reacting the ozone and thetetraethylorthosilicate at a temperature up to about 500° C. and apressure of at least about 10 torr to selectively deposit silicon oxideover the substrate surface and both the first conductive region and thesecond conductive region, whereby a greater thickness of silicon oxideis deposited on the first conductive region than on the secondconductive region; and, etching the silicon oxide deposited on thesubstrate to remove silicon oxide from the surface of the substrate,whereby the silicon oxide layers remaining on the first and secondconductive regions provides a layer of variable thickness around thefirst conductive region and the second conductive region.
 8. The methodof claim 7, wherein the reaction occurs at a temperature up to about400° C.
 9. The method of claim 7, wherein the reaction occurs at apressure of at least about 300 torr.
 10. A semiconductor processingmethod of fonning spacers of variable thickness, the method comprisingthe steps of: providing a silicon-comprising substrate having a surfacecomprising at least one first protrusion comprising either P-typesilicon or non-doped silicon and at least one second protrusion,provided that: (1) when the first protrusion comprises P-type silicon,then the second protrusion comprises either non-doped silicon or N-typesilicon; and, (2) when the first protrusion comprises non-doped silicon,then the second protrusion comprises N-type silicon; depositing siliconoxide, in a single process step, over the wafer surface and both thefirst protrusion and the second protrusion, whereby a greater thicknessof silicon oxide is deposited on the first protrusion than on the secondprotrusion; and, etching the silicon oxide deposited onl the substrateto remove silco oxide from the surface of the substrate, whereby thesilicon oxide layers remaining on the first and second protruionsprovides a layer of variable thickness around the first protrusion andthe second protrusion.
 11. A semiconductor processing method of formingspacers of variable thickness, the method comprising the steps of:providing a silicon-comprising substrate having a surface comprising atleast one first protrusion comprising either P-type silicon or non-dopedsilicon and at least one second protrusion, provided that: (1) when thefirst protrusion comprises P-type silicon, then the second protrusioncomprises either non-doped silicon or N-type silicon; (2) when the firstprotusion comprises non-doped silicon, then the second protrusioncomprises N-type silicon; decomposing tetraethylorthosilicate with ozoneto selectively deposit silicon oxide over the silicon surface and boththe first protrusion and the second protrusion, whereby a greaterthickness of silicon oxide is deposited on the first protrusion than onthe second protrusion; and, etching the silicon oxide deposited on thesubstrate to remove silicon oxide from the surface of the substrate,whereby the silicon oxide layers remaining on the first and secondprotrusions provides a layer of variable thickness around the firstprotrusion and the second protrusion.
 12. A semiconductor processingmethod of forming spacers of variable thickness, the method comprisingthe steps of: providing a silicon-comprising substrate having a surfacecomprising at least one first protrusion comprising either P-typesilicon or non-doped silicon and at least one second protrusion,provided that: (1) when the first protrusion comprises P-type siliconthen the second protrusion comprises either non-doped silicon or N-typesilicon; and, (2) when the first protrusion comprises non-doped siliconthen the second protrusion comprises N-type silicon; contacting thewafer surface with ozone and tetraethylorthosiicate whereby the firstprotrusion and the second protrusion are in intimate contact with theozone and the tetraethylorthosilicate; decomposing thetetraethylorthosilicate with the ozone to selectively deposit siliconoxide over the wafer surface and both the first protrusion and thesecond protrusion, whereby a greater thickness of silicon oxide isdeposited on the first protrusion than on the second protrusion; and,etching the silicon oxide deposited on the substrate to remove siliconoxide from the surface of the substrate, whereby the silicon oxidelayers remaining on the first and second protrusions provides a layer ofvariable thickness around the first protrusion and the secondprotrusion.
 13. A semiconductor processing.method of forming spacers ofvariable thickness, the process comprising the steps of: providing asilicoi-compnsing substrate having a surface comprising at least onefirst protrusion comprising either P-type silicon or non-doped siliconand at least one secondprotrusion, provided that: (1) when the firstprotrusion comprises P-type silicon then the second protusion compriseseither nonoped silicon or N-type silicon; and, (2) when the firstprotrusion comprises non-doped silicon, then the second protrusioncomprises N-type silicon; reacting ozone and the TEOS at a temperatureup to about 500° C. and a pressure of at least about 10 torr toselectively deposit silicon oxide over the wafer surface and both thefirst protrusion and the second protrusion, whereby a greater thicknessof silicon oxide is deposited on the first protrusion than on the secondprotrusion; and, etching the silicon oxide deposited on the substrate toremove silicon oxide from the surface, of the substrate, whereby thesilicon oxide layers remaining on the first and second protnisionsprovides a layer of variable thickness around the firt protrusion andthe second protrsion.
 14. The method of claim 13, wherein the reactionoccurs at a temperature up to about 400° C.
 15. The method of claim 13,wherein the reaction occurs at a pressure of at least about 300 torr.16. A semiconductot processing method of forming wordlines with spacersof vanable thickness, the process comprising the steps of: providing asilicon comprising substrate having a surface comprising at least onefirst wordline comprising P-type silicon and at least one secondwordline comprisnmg N-type silicon, the first and second wordlines beingseparated on the substrate; contacting the substrate with &zone andtetraethylorthosilicate whereby the first wordline and the secondwordline are in intimate contact with the ozone and thetetraethylorthosilicate; reacting the ozone and thetetraethylorthosilicate to selectively deposit silicon oxide over thesubstrate surface and both the first wordline and the second wordline,whereby a greater thickness of silicon oxide is deposited on the firstwordline then on the second wordline; and, etching the silicon oxidedeposited on the substrate to remove silicon oxide from the surface ofthe substrate, whereby the silicon oxide layers remaining on the firstand second wordlines provides a layer of variable thickness around thefirst wordline and the second wordline.
 17. A semiconductor processingmethod of forming wordlines with spacers of varable thickness, theprocess comprising the steps of: providing a silicon-comprisingsubstrate having a surface comprising at least one first wordlinecomprising P-type silicon and at least one second wordline comprisingN-type silicon: reacting ozone and tetraethylorthosilicate at atenperature up to about 500° C. and a pressure of at least about 10 torrto selectively deposit silicon oxide over the wafer surface and both thefirst wordline and the second wordline, whereby a greater thickness ofsilicon oxide is deposited on the first wordline than on the secondwordline; and, etching the silicon oxide deposited on the substrate toremove silicon oxide from the surface of the substrate, whereby thesilicon oxide layers remaining on the first and second wordlinesprovides a layer of variable thickness around the first wordline and thesecond wordline.
 18. The method of claim 11, wherein the reaction occursat a temperature up to about 400° C.
 19. The method of claim 11, whereinthe reaction occurs at a pressure of at least about 300 torr.
 20. Asemiconductor processing method of forming dual gate structures withspacers of variable thickness, the process comprising the steps of:providing a silicon comprising substrate having a surface comprising atleast one first gate comprising P-tppe silicon and at least one secondgate comprising N-type silicon: contacting the substrate with ozone andtetraethylorthosilicate whereby the first gate and the second gate arein intimate contact with the ozone and the tetraethylorthosilicate;reacting the ozone and the tetraethylorthosilicate to selectivelydeposit silicon oxide over the substrate surface and both the irst gateand the second gate, whereby a greater thickness of silicon oxide isdeposited on the first gate than on the second gate; and, etching thesilicon oxide deposited on the substrate to remove silicon oxide fromthe surface of the substrate, whereby the silicon oxide layers remainingon the first and second gatesprovides a layer of variable thicknessaround the first gate and the second gate.
 21. A semiconductorprocessing method of forming dual gate structures with spacers ofvariable thickness, the process comprising the steps of: providing asilicon comprising substrate having a surface comprising at least onefirst gate comprising P-type silicon and at least one second gatecomprising N-type silicon: reacting ozone and tetraethylorthosilicate ata temperature up to about 500° C. and a pressure of at least about 10torr to selectively deposit silicon oxide over the wafer surface andboth the first gate and the second gate, whereby a greater thickness ofsilicon oxide is deposited on the first gate than on the second gate;and, etching the silicon oxide deposited on the substrate to removesilicon oxide from the surface of the substrate, whereby the siliconoxide layers remaining on the first and second gates provides a layer ofvariable thickness around the first gate and the second gate.
 22. Themethod of claim 21, wherein the reaction occursat a temperatiire up toabout 400° C.
 23. The method of claim 21, wherein the reaction occurs ata pressure of at least about 300 torr.
 24. A semiconductor memory devicecomprising: at least one first wordline comprising P-tpe silicon orpolysilicon and a first nonconductive silicon oxide layer; at least onesecond wordline comprising N-tpe silicon or polysilicon and a secondnonconductive silicon layer; and wherein the first layer is thicker thanthe second layer.
 25. The semiconductor memory device of claim 25,wherein the first and second spacers are fonmed usingtetraethylorthosilicatel ozone deposition in a one step process.
 26. Thesemiconductor memory device of claim 25, wherein at least one of thefirst wordline or the second wordline form part of a DRAM array.
 27. Thesemiconductor memory device of claim 25 wherein The DRAM array is partof a system-on-chip.
 28. The semiconductor memory device of claim 25,wherein at least one of the fist wordline or the second wdrdline formpart ofan SRAM array.
 29. The semiconductor memory device of claim 25wherein the SRAM array is part of a system-on-chip.
 30. A multi-gatesemiconductor device comprising: at least one first P-type galesurrounded by a first nonconductive silicon oxide layer; and at leastone second N-type silicon gate surounded by a second nonconductivesilicon oxide layer; wherein the first nonconductive spacer is thickerthan the second nonconductive layer.
 31. The multi-gate semiconductordevice of claim 30, wherein the device is part of a logic circuit. 32.The multi-gate semiconductor device of claim 30, wherein the logiccircuit is part of a system-on-chip.
 33. A method for forming an oxidelayer of varying thickness on a silicon-comprising substrate, comprisingthe steps of: providing the silicon-comprising substrate having asurface and comprising at least a first region and a second region ofdifferent type conductivities; and depositing silicon oxide onto thesubstrate in a single process step, to form an oxide layer over thefirst and second conductivity regions; whereby the oxide layer overlyingthe second conductivity region is thicker than the oxide layer overlyingthe first conductivity region.
 34. The method of claim 33, wherein eachof the first and second regions comprise a structure formed on thesurface of the substrate, with a portion of the substrate intermediatethe structures having the oxide layer deposited thereon; and the methodfurer comprises the step of removing the oxide layer overlying thesubstrate between the first and second structures to expose the surfaceof the substrate.
 35. The method of claim 34, wherein the first andsecond structures comprise a silicon-comprising layer of a P-type orN-type conductivity, and an overlying salicide layer; whereby, when thesilicon-comprising layer of the first structure comprises a P-typeconductivity, the silicon-comprising layer of the second structurecomprises an N-type conductivity; and when the silicon-comprising layerof the first structure comprises an N-type conductivity, thesilicon-comprising layer of the second structure comprises a P-typeconductivity.